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Mr. Garg has over 24 years of experience in leading executive teams and managing companies across all stages of development and geographies. Mr. Garg incubated Tilera at Bessemer Venture Partners before founding the company in 2004. He served 4 years as the president and CEO and returned to Tilera in 2011. Under Mr. Garg’s leadership, Tilera released the industry leading TILE-Gx family of processors, including the 64bit TILE-Gx72 - the world’s highest performance, highest efficiency embedded processor. Since his return, Mr Garg has led the team in delivering global success through a well-defined strategy resulting in customer design wins (>100), revenue growth (>3x), and crisp companywide execution.
Tilera received the prestigious Start-Up of the Year award from the Global Semiconductor Association (GSA) in 2008 and also has been recognized as one of the Top 50 most innovative companies in the world. Furthermore, Tilera received the ACE Award for the Best Design Team in 2012 from EE Times.
Prior to returning to Tilera, Mr. Garg served as a Managing Director of Bessemer Venture Partners where he actively managed and advised investments in PA Semi (acquired by Apple Computer), Azanda (acquired by Cortina), K2 Optronics (acquired by Emcore), Berkeley Design Systems and Avnera. Mr. Garg has Asian international experience having lived in Mumbai, India for 3+years investing and managing a wide range of companies prior to returning to the United States.
Before joining Tilera, Mr. Garg was General Manager of the Security Business Unit at Broadcom (Nasdaq: BRCM), where he was part of the pre-IPO team, establishing Broadcom’s first offices in Northern California. With executive management responsibilities for technical sales and field application engineering, he led his division from its inception to ~$500 million in annual revenues as Broadcom grew from a start-up to its peak market capitalization of approximately $72 billion while acquiring 22 companies during that time. Previously, Mr. Garg led the sales team at Synopsys, and served in engineering and managerial positions at LSI Logic, National Semiconductor, Bechtel, and Raychem. Mr. Garg holds a B.S.E.E. from San Jose State University and an M.B.A. from Santa Clara University.
Mr. Rava has over 25 years of experience in the semiconductor industry, having served in a variety of sales executive positions. Most recently, Mr. Rava was VP of WW Sales and Applications at Cavium Networks for 9 years where he built, managed and was responsible for the 150 person global field team that generated $300M in annual revenues and the associated design wins. He was at Cavium in the early days and also served as the sales executive overseeing their global field team up through IPO and beyond.
Mr. Rava has also held executive sales management roles at Vitesse Semiconductor where he was VP of WW Sales for the Ethernet Products Division and with Broadcom for 3 years by way of the acquisition of Altima Communications. While at Broadcom he was part of the team that managed the overall Cisco relationship that generated up to ~$500M annually. He was integral in the sale of L2/L3 Ethernet switches and the 10/100/1000 Base-T physical layer transceivers (‘PHYs’) to the Desktop Switching Business Unit (market leader with ~65% market share of wiring closet switches). This business ultimately was the cornerstone of what is now the entire networking line of business within Broadcom.
While at Altima, Mr. Rava was Director of Sales for North America and Europe. Altima produced networking integrated switch ICs optimized for the cost-sensitive SMB customer, with an emphasis on low-power, small footprint, and low system cost. Mr. Rava has also held various positions at Disco Corporation, Burr Brown and Medianics (DSPs for multi-media and consumer electronics).
He has a BA and MBA from Lasalle University and has also completed coursework at Stanford University in advanced project management.
Mr. Mattina has over 15 years of experience designing and architecting high-end CPUs and multicore processors. Prior to Tilera, Mr. Mattina was with Intel Corporation where he was co-lead architect for the Tukwila Multicore Processor, supervising a team of architects and designers. At Intel, Mr. Mattina invented and designed the Intel Ring Uncore Architecture, used across Intel’s x86 multicore processor designs. This technology won the Intel Achievement Award in 2010. Prior to Intel, he was an architect and circuit design engineer at Digital Equipment Corporation, working on the Alpha EV7 and EV8 processors. Mr. Mattina also served as Technical Leader at Cisco Systems in the TelePresence Infrastructure Business Unit, where he contributed to the hardware and software design of next-generation high-definition video conferencing products. He has been granted over 20 patents and has published journal and conference papers relating to CPU design, multicore processors, and cache coherence protocols. Mr. Mattina holds a BS in Computer and Systems Engineering (Summa Cum Laude) from Rensselaer Polytechnic Institute and a MS in Electrical Engineering from Princeton University.
Mr. Brown has over 25 years of experience in CPU architecture and processor design. Previously, as an AMD Fellow, he led an architecture team targeting the Athlon 64 (for desktop), Turion (for mobile), and Sempron (value mobile/desktop). Prior to that, Mr. Brown was Director of Logic and Architecture at C-Port Corporation, producing the C5 Network Processor. C-Port was acquired by Motorola in 2000. From 1980-1998 John worked at Digital Semiconductor where he contributed to the VAX 8200, VAX 6400, VAX 6600, Alpha 21066, and Alpha 21264 microprocessor designs and architecture, and directed architecture development for future Alpha designs. Mr. Brown managed the design team for the Alpha 21066, the microprocessor powering the Multia MultiClient that won NT desktop product of the year. He holds nine patents and has authored several publications related to CPU architecture and design verification. Mr. Brown holds a BS in Electrical Engineering and a MS in Electrical Engineering from Cornell University.
Mr. Schooler has more than 20 years of experience in technical leadership and engineering management in the software industry, primarily in programming language implementation, program transformation, and performance optimization. Before coming to Tilera, he was Director of Windows Build for Microsoft Corporation. Mr. Schooler has served as a Technical Director at VERITAS Software, Vice President of Technology at Geodesic Systems, the Chief Technology Officer for InCert Software, and in project management and software engineering roles at Hewlett Packard, Bolt Beranek & Newman Advanced Computers, and Intermetrics. He has been granted five patents and has published technical papers in compiler implementation and program optimization. Mr. Schooler holds a BS in Computer Science and Mathematics and a MS in Computer Science from the Massachusetts Institute of Technology.
Mr. Moore has more than 20 years of microprocessor industry experience in both engineering and operations roles, bringing a unique combination of expertise from both a supplier and customer’s perspective. At Tilera, Mr. Moore is in charge of global operations focusing on enhancing worldwide practices as the company continues to grow and expand. He adds an exceptional executive experience to Tilera’s semiconductor and platform operations organization.
Prior to joining Tilera, he spent five years at Apple Inc. managing key silicon suppliers to meet high quality supply and manufacturability standards in the Mac hardware division, as well as integrating multiple generations of chipset and GPU devices into Apple's platforms. Prior to Apple, Mr. Moore was director of operations design at Montalvo Systems where he established the operations team for their multi-core x86 processor and drove the business and technical engagements with the foundry, assembly, and test partners across a global footprint. Mr. Moore also spent nine years at Transmeta Corp. working on a family of lowpower microprocessors, holding various management positions in product and test engineering that helped lead to a successful IPO in 2001. He began his career at Texas Instruments working on a family of mixed-signal micro-controllers for automotive applications, engaged in design, product and test engineering, and program management.
Mr. Moore holds a BSEE from the University of Cincinnati, and an MBA from Santa Clara University.
Mr. Aggarwal joined Tilera in October 2004 with more than 25 years of experience in systems engineering including in all aspects of hardware, software and system architectures. Mr. Aggarwal was the CTO and founder of Gotham Networks where he was responsible for architecture and design of the first network processor-based Multi-Service Switching Platform (MSSP). He was elected to MPLS forum's board. Previously Mr. Aggarwal was a system architect at Nexabit Networks where he was responsible for the first round of terabit router architectures and system design. Nexabit was sold to Lucent Technologies. Mr. Aggarwal has experience with Cisco, Lightream, Cascade, and BBN. He has authored six patents in the area of high speed network processing. Mr. Aggarwal holds a BS in Electrical Engineering from University College Dublin, Ireland.
Mr. Dexter brings over 25 years of financial leadership and experience in both start-ups and multi-billion dollar global firms. Just prior to joining Tilera, Mr. Dexter was VP of Finance and Controller of RMI Corporation until its acquisition by NetLogic Microsystems. While there, he led the financial effort to both scale and prepare RMI for a public offering. Prior to joining RMI, Neil held CFO positions at Oraxion, OneChannel, and Protexis. Mr. Dexter, also served as VP of Finance and Treasury for PB/NEC, the multi-billion dollar PC developer and manufacturer, where he had global responsibility for the three areas of Treasury, Corporate Financial Planning and Analysis and Reporting, as well as the Consumer Division financial support. Prior to PB/NEC Mr. Dexter held executive finance positions at Zenith Data Systems and Olivetti’s North America’s subsidiary. Mr. Dexter’s career began at IBM in both Canada and the US. He has an MBA from the University of Toronto and a BS in Industrial Economics, combining engineering and economics, from Union College in New York.
Mrs. Dunnigan has over 20 years of experience developing and leading HR strategy initiatives and supporting management teams in the semiconductor industry. Prior to joining the company Mrs. Dunnigan was a Senior Consultant at Torchiana, Mastrov and Sapiro, a career management firm that provides individual and group outplacement, executive career coaching, and career development programs. Mrs. Dunnigan has also served in global HR management roles for Aptina, Motorola Semiconductor, now Freescale, where she held positions of increasing responsibility until 2006. During her time at Motorola she completed a three-year international assignment in East Kilbride, Scotland, where she was responsible for supporting the wafer manufacturing teams and implemented the organization's first operator testing and assessment processes. Mrs. Dunnigan received a Bachelor of Science in Human Resources Management from Arizona State University and is an active member of the Society of HR Management and the Northern California HR Association.