Management

Devesh Garg, Co-Founder, President, and Chief Executive Officer

Mr. Garg has over 23 years of experience in leading executive teams and managing companies across all stages of development and geographies. He served for 4 years as Tilera's founding president and CEO during which time he defined the strategy and vision, taking the company from its incubation at Bessemer Venture Partners through its outsider-led, over-subscribed B-round. In 2007, Mr. Garg launched the TILE64 processor and lead the team in driving customer design wins and revenue. Tilera received the prestigious Start-Up of the Year award from the Global Semiconductor Association (GSA) in 2008.

Most recently Mr. Garg was Managing Director of Bessemer Venture Partners where he actively managed and advised Bessemer's investments in Azanda (acquired by Cortina), K2 Optronics (acquired by Emcore) and PA Semi (acquired by Apple Computer). Mr. Garg lived in India for three years advising and investing in a wide range of companies prior to returning to the United States.

Before joining Tilera, Mr. Garg was General Manager of the Security Business Unit at Broadcom (Nasdaq: BRCM), where he was part of the pre-IPO team and established their offices in Northern California. With executive management responsibilities for technical sales and field application engineering, he led his division to ~$500 million in annual revenues from nothing as the company grew from a start-up to its peak market capitalization of approximately $72 billion. Previously, Mr. Garg led the sales team at Synopsys, and served in engineering and managerial positions at LSI Logic, National Semiconductor, Bechtel, and Raychem. Mr. Garg holds a B.S.E.E. from San Jose State University and an M.B.A. from Santa Clara University.

Anant Agarwal, Co-Founder and Chief Technology Officer

Dr. Agarwal is also a professor of Electrical Engineering & Computer Science at MIT, and an associate director of the MIT CSAIL Laboratory. Dr. Agarwal served as Associate Director of the MIT Laboratory for Computer Science (LCS) between 1998 and 2003, and was a co-leader of the Oxygen Project. He led a group that developed Sparcle (1992), an early multi-threaded microprocessor based on the SPARC architecture, and the Alewife machine, a scalable shared-memory multiprocessor (1993). At MIT's CSAIL laboratory, Dr. Agarwal led the Raw project, which developed a tiled multicore microprocessor for instruction level parallelism (ILP) and streams (2002). Dr. Agarwal also led the VirtualWires project at MIT. He has been a founder of several successful start-ups, including Virtual Machine Works, Inc. (1993). Dr. Agarwal won the Maurice Wilkes prize for computer architecture in 2001, the Presidential Young Investigator award in 1991, and the Louis D. Smullin Award for teaching excellence at MIT in 2005. Dr. Agarwal holds a bachelor's from IIT Madras (1982) and a Ph.D. (1987) in Electrical Engineering from Stanford University.

Michael Zimmerman, Vice President of Marketing

Mr. Zimmerman has over 20 years experience in semiconductor marketing and product management. Prior to joining Tilera he served as VP CPU System On Chip group with Marvell where he was responsible for next generation Multicore ARM CPU targeted at the carrier edge, servers and public cloud infrastructure. Before Marvell, Michael served in a VP role for ADC Telecommunications, Broadband division, responsible for the Broadband Access portfolio. Among other broadband initiatives, Michael participated in the Broadband Forum, serving as editor chair for several working texts and driving multimedia xDSL market adoption. Prior to ADC, Michael served as System Architect with Nortel Networks, responsible for broadband access portfolio. Mr. Zimmerman holds a BSEE (Summa Cum Laude) from Tel Aviv University and a M.B.A. (Dean List) Tel Aviv University.

Vijay Aggarwal, Co-Founder and Vice President of Business Development

Mr. Aggarwal joined Tilera in October 2004 with more than 25 years of experience in systems engineering including in all aspects of hardware, software and system architectures. Mr. Aggarwal was the CTO and founder of Gotham Networks where he was responsible for architecture and design of the first network processor-based Multi-Service Switching Platform (MSSP). He was elected to MPLS forum's board. Previously Mr. Aggarwal was a system architect at Nexabit Networks where he was responsible for the first round of terabit router architectures and system design. Nexabit was sold to Lucent Technologies. Mr. Aggarwal has experience with Cisco, Lightream, Cascade, and BBN. He has authored six patents in the area of high speed network processing. Mr. Aggarwal holds a BS in Electrical Engineering from University College Dublin, Ireland.

Nagaraj Murthy, Vice President of Operations

Mr. Murthy has more than 16 years of silicon manufacturing and operational management experience. Most recently he was VP of Operations at Greenfield Networks, which was acquired by Cisco. Mr. Murthy served in senior operational and engineering roles at Silicon Access where he drove the productization of the first 40Gb core networking chipset. Prior to that he was at ATI, through the acquisition of Chromatic research where he was responsible for development and production of multiple generations of graphic chips. Mr. Murthy also was with Sun Microsystems where he was responsible for bringing complex ASICs and the SPARC Microprocessors to market. Mr. Murthy holds a BS in Engineering from Madras University, India, and a MS in Electrical Engineering from the University of Texas, Austin.

John F. Brown III, Vice President of IC Engineering

Mr. Brown has over 25 years of experience in CPU architecture and processor design. Previously, as an AMD Fellow, he led an architecture team targeting the Athlon 64 (for desktop), Turion (for mobile), and Sempron (value mobile/desktop). Prior to that, Mr. Brown was Director of Logic and Architecture at C-Port Corporation, producing the C5 Network Processor. C-Port was acquired by Motorola in 2000. From 1980-1998 John worked at Digital Semiconductor where he contributed to the VAX 8200, VAX 6400, VAX 6600, Alpha 21066, and Alpha 21264 microprocessor designs and architecture, and directed architecture development for future Alpha designs. Mr. Brown managed the design team for the Alpha 21066, the microprocessor powering the Multia MultiClient that won NT desktop product of the year. He holds nine patents and has authored several publications related to CPU architecture and design verification. Mr. Brown holds a BS in Electrical Engineering and a MS in Electrical Engineering from Cornell University.

Richard Schooler, Vice President of Software Engineering

Mr. Schooler has more than 20 years of experience in technical leadership and engineering management in the software industry, primarily in programming language implementation, program transformation, and performance optimization. Before coming to Tilera, he was Director of Windows Build for Microsoft Corporation. Mr. Schooler has served as a Technical Director at VERITAS Software, Vice President of Technology at Geodesic Systems, the Chief Technology Officer for InCert Software, and in project management and software engineering roles at Hewlett Packard, Bolt Beranek & Newman Advanced Computers, and Intermetrics. He has been granted five patents and has published technical papers in compiler implementation and program optimization. Mr. Schooler holds a BS in Computer Science and Mathematics and a MS in Computer Science from the Massachusetts Institute of Technology.

Neil Dexter, Vice President of Finance and Controller

Mr. Dexter brings over 25 years of financial leadership and experience in both start-ups and multi-billion dollar global firms.  Just prior to joining Tilera, Mr. Dexter was VP of Finance and Controller of RMI Corporation until its acquisition by NetLogic Microsystems. While there, he led the financial effort to both scale and prepare RMI for a public offering. Prior to joining RMI, Neil held CFO positions at Oraxion, OneChannel, and Protexis. Mr. Dexter, also served as VP of Finance and Treasury for PB/NEC, the multi-billion dollar PC developer and manufacturer, where he had global responsibility for the three areas of Treasury, Corporate Financial Planning and Analysis and Reporting, as well as the Consumer Division financial support. Prior to PB/NEC Mr. Dexter held executive finance positions at Zenith Data Systems and Olivetti’s  North America’s subsidiary. Mr. Dexter’s career began at IBM in both Canada and the US. He has an MBA from the University of Toronto and a BS in Industrial Economics, combining engineering and economics, from Union College in New York.