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About Tilera

The Tile Processor architecture is a significant step in the decades-long pursuit to harness the power of multiple processors and meet the performance requirements of executing compute intensive applications. The architecture has evolved to become the first design incorporating large numbers of full featured general purpose programmable processors on a single chip.

Early efforts by computer scientists relied on backplane or cluster technologies to connect multiple processors. One such effort was the Alewife project at MIT, led by Tilera CTO, Dr. Anant Agarwal in 1990. The Alewife project resulted in the development of a scalable multi-processor system built out of large numbers of single chip processors. Alewife machines integrated both shared memory and user-level message passing for inter-node communications. The machines demonstrated a pioneering 32-node mesh based cache-coherent multiprocessor.

In 1995, Dr. Agarwal founded Virtual Machine Works (now part of Mentor Graphics), which solved logic emulation by combining 100's of FPGA's using a mesh interconnect and a patented 'virtual wires' compiler.

In 1997, Dr. Agarwal proposed a follow-on project using a mesh technology to connect multiple cores. The follow-on project, RAW, which commenced in 1997, and was supported by DARPA/NSF's funding of tens of millions, resulting in the world's first 16-processor tiles multicore and proving the mesh and compiler technology. The 16 cores were connected in a 4x4 mesh and were integrated onto one piece of silicon. The RAW processor enabled the seamless scaling of processors by connecting them via a 2D interconnection fabric. RAW chips could be gluelessly connected to make larger fabrics of processors - up to 1024 cores. The RAW processor was able to manage inter-processor communication of very large as well as very small quanta of data with extremely low latency and high bandwidth.

Tilera: A Rich Heritage

By 2004, Dr. Agarwal had demonstrated the functionality of the RAW processor to both ISSCC and ISCA. Recognizing the commercial potential for the technology, Dr. Agarwal licensed the technology from MIT, and together with Vijay Aggarwal as VP of Business Development, and Devesh Garg as CEO, founded Tilera Corporation, and began drawing on the talent of many members of the original RAW team to architect the next generation multicore processor.

In 2005 and after securing its first round of funding, Tilera pulled in top talent from industry leading companies to start developing the TILE64 processor and the Multicore Development Environment. The execution-oriented team developed silicon and software, and shipped the first release in 2007 delivering the industry's highest performance embedded processor and an unmatched development environment. It was at this point that Omid Tahernia joined the team as CEO. With more than 20 years experience in semiconductors and embedded systems, Mr Tahernia was selected as the leader to guide the company to production and profitability.

With several design wins and the production release of the TILE64 in 2008, Tilera continued the drive for innovation and released the second generation of production processors, the TILEPro family. The TILEPro64 and the TILEPro36 offer both higher performance and a solution for lower tier products.

In 2009, despite the challenging economic environment, Tilera secured it's third round of funding and continued to amass design wins. The company also announced it's third generation of TILE processors, the Gx family, with 16, 36, 64, and 100 core versions. Based on customer feedback and ongoing research, Tilera imbued this new generation of processors with increased performance and reduced power requirements further securing the company's leadership in high performance, low power computing.