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TILE-Gx Processor Family

The TILE-Gx™ processor family brings 64-bit multicore computing to the next level, enabling a wide range of applications to achieve the highest performance in the market.

This latest generation processor family features devices with 16 to 100 identical processor cores (tiles) interconnected with Tilera's iMesh™ on-chip network. Each tile consists of a complete, full-featured processor as well as L1 and L2 cache and a non-blocking switch that connects the tiles into the mesh. As with all Tilera® processors, each tile can independently run a full operating system, or multiple tiles taken together can run a multiprocessing OS like SMP Linux.

The TILE-Gx family processor slashes board real estate requirements and system costs by integrating a complete set of memory and I/O controllers, eliminating the need for an external north bridge or south bridge. TileDirect™ technology provides coherent I/O directly into the tile caches to deliver ultimate low-latency packet processing performance. Tilera's DDC™ (Dynamic Distributed Cache) system for fully coherent cache across the tile array enables scalable performance for threaded and shared memory applications.

The TILE-Gx processors are programmed in ANSI standard C and C++, enabling developers to leverage their existing software investment. Tiles can be grouped in clusters to apply the appropriate amount of horsepower to each application. Since multiple, virtualized operating system instances can be run on the TILE-Gx simultaneously, it can replace multiple CPU and DSP subsystems for both the data plane and control plane.

Applications

Cloud Computing

  • Web Applications (LAMP)
  • Data Caching (memcached)
  • Database Applications
  • High-Performance Computing (HPC)
 

Digital Video

  • Video Transcoding/Transrating
  • Videoconferencing MCU and Endpoints
  • Streaming IPTV and Video-on-Demand
  • Video Post-Production Processing

Wireless Infrastructure

  • Base Transceiver Station (BTS)
  • Base Station Controllers (BSC)
  • Wireless Backbone Gateways (GGSN, MGW)
 

Advanced Networking

  • Firewall & VPN
  • Intrusion Detection and Prevention (IDS/IPS)
  • Unified Threat Management (UTM)
  • L4-7 Deep Packet Inspection
  • Network Monitoring and Forensics
 FeatureEnables

Massively Scalable Performance

  • An array of 16 to 100 general-purpose processor cores (tiles)
  • 64-bit VLIW processors with a 64-bit instruction bundle
  • Three-way pipeline with up to three instructions per cycle
  • 32K L1i cache, 32K L1d cache, 256K L2 cache per tile
  • Up to 750 billion operations per second (BOPS)
  • Up to 200 Tbps of on-chip mesh interconnect
  • Over 500 Gbps memory bandwidth with four 64-bit DDR3 controllers
  • 40 - 80 Gbps Snort® processing
  • 40 - 80 Gbps nProbe
  • H.264 HD video encode: dozens of streams of 1080p (baseline profile)
  • 64+ channels of OFDM baseband receiver processing (wireless)

Power Efficiency

  • 1.0 to 1.5GHz operating frequency
  • 10 to 55W for typical applications
  • Idle Tiles can be put into low-power sleep mode
  • Power efficient inter-tile communications
  • Highest performance per watt
  • Simple thermal management and power supply design
  • Small system form factor
  • Lowest operating cost

Integrated Solution

  • Four DDR3 memory controllers with optional ECC
  • Up to eight 10GbE XAUI interfaces; two Interlaken interfaces
  • Three Gen2 PCIe interfaces, each selectable as endpoint or root complex
  • Three StreamIO™ ports, each providing up to 20Gbps throughput for Tile-to-Tile or FPGA interconnect
  • Up to 32 GbE MAC interfaces
  • Wire-speed mPIPE™ packet processing engine
  • On-chip hardware encryption and compression(MiCA™)
  • Reduces BOM cost - standard interfaces on-chip
  • Dramatically reduced board real estate
  • Up to 80 Gbps PCIe bandwidth
  • Over 80 Gbps of packet I/O bandwidth
  • Up to 40 Gbps VPN performance

Ease of Programming

  • GCC compiler (C / C++)
  • Advanced profiling and debugging designed for multicore programming
  • Supports SMP Linux and virtualization
  • TMC libraries for efficient inter-tile communication
  • Run off-the-shelf C and C++ programs
  • Leverage investment in existing code
  • Standard multicore communication mechanisms
  • Reduce debug and optimization time
  • Faster time to production code

TILE-Gx Diagram

TILE-Gx™ Processor Block Diagram

 TILE-Gx100TILE-Gx64TILE-Gx36TILE-Gx16
Number of Cores100643616
Core Frequency1.2, 1.5GHz1.0 1.2GHz1.0, 1.2GHz1.0, 1.2GHz
Network Interface2x 50G Interlaken
8 XAUI, 32 SGMII		2x 50G Interlaken
6 XAUI, 24 SGMII		—
4 XAUI, 16 SGMII		—
2 XAUI, 12 SGMII
PCIeThree 8-laneThree 8-laneOne 8-lane
Two 4-lane		—
Three 4-lane
DDR3 Controllers4422
DDR3 Frequency1866 MT/s1866 MT/s1866 MT/s1333 MT/s
Package45 x 45mm BGA45 x 45mm BGA37.5 x 37.5mm BGA37.5 x 37.5mm BGA