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The TILEPro™ processor family brings multicore computing to the next level, enabling embedded applications to achieve the highest compute performance in the market.

The TILEPro™ processor features either 36 or 64 identical processor cores (tiles) interconnected with Tilera's iMesh™ on-chip network. Each tile consists of a complete, full-featured processor as well as L1 and L2 cache and a non-blocking switch that connects the tiles into the mesh. The TILEPro™ family incorporates Tilera's Dynamic Distributed cache (DDC™) technology that accelerates coherent cache performance by a factor of two compared with other multicores. As with all Tilera processors, each tile can independently run a full operating system, or multiple tiles grouped together can run a full multi-processing OS like SMP Linux.

The TILEPro™ processor slashes board real estate and system costs by integrating a complete set of memory and I/O controllers, therefore eliminating the need for an external north bridge or south bridge. New TileDirect™ technology provides coherent I/O directly into the tile caches to deliver ultimate low-latency packet processing performance.